Processing of data for digital logic or communications applications generally requires a clock source at the frequency of the data. Ring oscillators have been widely used as high frequency clock sources, especially in phase-locked loop (PLL) applications where they may be used to multiply the frequency of a stable low frequency clock source. Ring oscillators are used due to their ease of design and very low silicon area when integrated on a chip. Conventional ring oscillators use an odd number of inversions to achieve stable oscillation. This suggests either an odd number of stages in the oscillator or use of a fully differential circuit design for each stage. Use of a fully differential circuit for each stage increases circuit area and is undesirable in some applications.
Clock sources often must be able to produce quadrature outputs, not just true and complement outputs. Two outputs are in quadrature when one is phase shifted by about one quarter of a period with relation to the other. When a ring oscillator has an odd number of stages, it is difficult to produce two outputs in quadrature (without additional circuitry). Therefore it is desirable to have an even number of stages in the ring oscillator, which is not generally possible with conventional designs other than differential circuit designs.
Array oscillator techniques have been applied to solve this problem. A recent example was published at the European Solid-State Circuits Conference 2003 (ESSCIRC 2003) entitled “CMOS Ring Oscillator with Quadrature Outputs and 100 MHz to 3.5 GHz Tuning Range” by M. Grozing et al. Their scheme is shown in FIG. 1, using eight identical CMOS inverter stages connected in a feed-forward array. The feed-forward inverters allow the normal four stage ring to oscillate and speed up the frequency. Since it is a ring with four identical output nodes, successive nodes are generally in quadrature.
This scheme as shown in FIG. 1 does not show any means for varying the frequency of oscillation, which is highly desired, if not required, for many PLL applications. Grozing et al. used the circuit shown in FIG. 2 for each inverter pair. The circuit of FIG. 2 represents, for example, inverters 102 and 106 in FIG. 1. P-channel bias transistor 203 and n-channel bias transistor 204 control (or “steer”) the current available to turn a successive stage on and off, thus controlling the circuit delay and thus the frequency of the oscillator.
The current steering technique has two undesirable attributes. First, as the current changes, the up and down levels of the signals change. An output circuit which can respond to this varying level may need to be included in the oscillator. As the signal level gets lower, the noise also increases. The second undesirable attribute is that the frequency control voltage applied to the p-channel bias transistor 203 is generally different from the frequency control voltage applied to the n-channel bias transistor 204, but is generally related by a constant which is affected by manufacturing variations in transistor parameters. Grozing et al. teach the use of voltage regulator circuits to adjust the two control voltages.
From the above discussion it is apparent that simple circuits using standard CMOS inverter stages in an array oscillator configuration is desirable. It is also desirable to be able to control the frequency of the array oscillator using a single control voltage.